DFT Engineer - SoC/ASIC

Key Responsibilities : 1. Define and implement DFT architecture and strategy for complex SoCs or ASICs. 2. Develop and integrate scan, ATPG, BIST (LBIST/MBIST), and boundary scan logic. 3. Generate test patterns and perform fault grading, coverage analysis, and test compression. 4. Work with RTL and physical design teams to ensure DFT logic integration and timing closure. 5. Support silicon bring-up, test vector validation, and ATE support. 6. Collaborate with verification and validation teams to ensure testability goals are met. 7. Optimize DFT methodologies for yield, performance, and power. Requirements : 1. Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 2. 6 years of experience in DFT implementation for ASIC/SoC designs. 3. Strong knowledge of scan insertion, ATPG, MBIST, LBIST, and JTAG standards. 4. Experience with industry-standard EDA tools (e.g., Synopsys DFT Compiler, Tetramax, Mentor Tessent). 5. Familiarity with RTL design (Verilog/System Verilog) and scripting languages (TCL, Perl, Python). 6. Knowledge of ATE concepts and experience with silicon debug is a plus. 7. Excellent communication and teamwork skills. (ref:hirist.tech)

Location: hyderabad, IN

Posted Date: 4/29/2025